1. Technical Field
Various examples of embodiments may generally relate to a memory system including a memory controller and a memory buffer chip, and more particularly, to a memory controller, a memory buffer chip, a memory system, and method of operating or controlling the same.
2. Related Art
FIG. 1 is a block diagram illustrating a conventional memory system.
The conventional memory system consists of a memory controller 10, a memory buffer chip 20 and a plurality of memory chips 30.
The memory buffer chip 20 and the plurality of memory chips 30 may be included in one memory module.
The conventional memory system consists of the memory buffer chip 20 which is installed between the memory controller 10 and the memory chips 30 in order to improve the signal quality, when a plurality ranks RANK are coupled to one channel.
The memory buffer chip 20 buffers a command/address/data.
In general, the synchronous interface technology is used to simplify design. According to the synchronous interface technology, an operating frequency between the memory controller 10 and the memory buffer chip 20 is equal to an operating frequency between the memory buffer chip 20 and the memory chip 30.
However, the two frequencies may not be equal to each other due to various reasons. For example, when a high capacity is intended to be implemented at one channel, the two frequencies may be different from each other.
In addition, when the number of ranks coupled to one channel is increased, speed degradation may occur to cause a difference between the operating frequencies.
Furthermore, a memory chip with a low operating frequency may be intentionally used for the yield or low power consumption.
Moreover, when speed provided by a new type of memory chip has a limit, a difference may occur between the operating frequencies.
As such, the two operating frequencies may have a difference therebetween due to various reasons. In order to compensate for a difference between the operating frequencies while maintaining the synchronous interface technology, the level of difficulty in the overall design of the memory system inevitably increases. For example, the memory controller must be designed to correct a timing parameter.
Therefore, there is a demand for a new memory system which does not raise the level of difficulty in design even though a difference occurs between operating frequencies.